Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

Flash read issues leading to wrong instruction fetch or incorrect data read may occur under the following operating 

conditions:
VDDIO < 2.4V and Flash wait state

 ≥ 1

If the core clock frequency does not require the use of the Flash wait state 

 (FWS = 0 in EEFC_FMR) or if only data 

reads are performed on the Flash (e.g., if the code is running out of SRAM), there are no constraints on VDDIO voltage. 

.

Notes:

1. Defined by the FWS field in EEFC_FMR register.
2. See 

 for the maximum core clock frequency at zero (0) wait 

state.

Two workarounds are available:

1. Reduce the device speed to decrease the number of wait states to 0.
2. Copy the code from Flash to SRAM at 0 wait states and then run the code out of SRAM.

The issue will be corrected in the next device revision, Marketing Revision Level B (MRL B). Please contact your local 

Sales Representative for further details.

The sequence below leads to a bad read value.
Fail sequence is:

Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address XXX

A dummy read at another address needs to be included in the sequence.
Sequence is:

Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address YYY (dummy read)
Read Flash @ address XXX 

When the Watchdog is enabled and the bit WAITMODE = 1 is used to enter wait mode, the watchdog is not halted. If the 

time spent in Wait Mode is longer than the Watchdog time-out, the device will be reset if Watchdog reset is enabled.

When entering wait mode, the Wait For Event (WFE) instruction of the processor Cortex-M4 must be used with the 

SLEEPDEEP of the System Control Register (SCB_SCR) of the Cortex-M = 0.