Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
151
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
12.6.6.6 SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
where:
opis one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
SMLAW Signed Multiply Accumulate (word by halfword).
If X is present, the multiplications are bottom × top and top × bottom.
opis one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
SMLAW Signed Multiply Accumulate (word by halfword).
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
condis an optional condition code, see
condis an optional condition code, see
.
Rdis the destination register.
Rn, Rmare registers holding the first and second operands.
Rais the register holding the accumulate value.
Operation
The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This
Rn, Rmare registers holding the first and second operands.
Rais the register holding the accumulate value.
Operation
The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This
instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the signed accumulate value to the result of the subtraction.
Writes the result of the addition to the destination register.
The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords.
This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.
Writes the 64-bit result of the addition to the RdHi and RdLo.
Restrictions
In these instructions:
In these instructions:
Do not use SP and do not use PC.
Condition Flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the
multiplications or subtraction.
For the Thumb instruction set, these instructions do not affect the condition code flags.
Examples
For the Thumb instruction set, these instructions do not affect the condition code flags.
Examples