Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

190

Data Synchronization Barrier.
Syntax

DSB{cond}

where:
condis an optional condition code, see 

.

Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program 

order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory 

accesses before it complete.
Condition Flags
This instruction does not change the flags.
Examples

DSB ; Data Synchronisation Barrier 

Instruction Synchronization Barrier.
Syntax

ISB{cond}

where:
condis an optional condition code, see 

.

Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions 

following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.
Condition Flags
This instruction does not change the flags.
Examples

ISB

; Instruction Synchronisation Barrier