Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The System Control Block (SCB) provides system implementation information, and system control. This includes 

configuration, control, and reporting of the system exceptions.
Ensure that the software uses aligned accesses of the correct size to access the system control block registers:



Except for the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it must use aligned word accesses



For the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it can use byte or aligned halfword or word 

accesses.

The processor does not support unaligned accesses to system control block registers.
In a fault handler, to determine the true faulting address:

1. Read and save the MMFAR or SCB_BFAR value.

2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The 

SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1.

The software must follow this sequence because another higher priority exception might change the SCB_MMFAR 

or SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault 

might change the SCB_MMFAR or SCB_BFAR value.