Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

209

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

SCB_ACTLR

 Read

/Write

 0x00

0000000

The SCB_ACTLR provides disable bits for the following processor functions:

• IT folding

• Write buffer use for accesses to the default memory map

• Interruption of multi-cycle instructions.

By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally 

require modification.

Disables floating point instructions that complete out of order with respect to integer instructions.

Disables an automatic update of CONTROL.FPCA.

When set to 1, disables the IT folding.

Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. 

This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must 

avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding.

When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise 

but decreases the performance, as any store to memory must complete before the processor can execute the next 

instruction.
This bit only affects write buffers implemented in the Cortex-M4 processor.

When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the interrupt 

latency of the processor, as any LDM or STM must complete before the processor can stack the current state and enter the 

interrupt handler.

31

30

29

28

27

26

25

24

–

23

22

21

20

19

18

17

16

–

15

14

13

12

11

10

9

8

–

DISOOFP

DISFPCA

7

6

5

4

3

2

1

0

–

DISFOLD

DISDEFWBUF

DISMCYCINT