Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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Write:
0: No effect.
1: Removes the pending state from the PendSV exception.

Write:
0: No effect.
1: Changes SysTick exception state to pending.
Read:
0: SysTick exception is not pending.
1: SysTick exception is pending.

Write:
0: No effect.
1: Removes the pending state from the SysTick exception.
This bit is Write-only. On a register read, its value is Unknown.

0: Interrupt not pending.
1: Interrupt pending.

0: No pending exceptions.
Nonzero: The exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the 

PRIMASK register.

0: There are preempted active exceptions to execute.
1: There are no active exceptions, or the currently-executing exception is the only active exception.

0: Thread mode.
Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See 

.

Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-

Pending, Set-Pending, or Priority Registers, see 

Note: When the user writes to the SCB_ICSR, the effect is unpredictable if:

- Writing a 1 to the PENDSVSET bit and writing a 1 to the PENDSVCLR bit

- Writing a 1 to the PENDSTSET bit and writing a 1 to the PENDSTCLR bit.