Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
213
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
12.9.1.4 Vector Table Offset Register
Name:
SCB_VTOR
Access:
Read
/Write
Reset:
0x00
0000000
The SCB_VTOR indicates the offset of the vector table base address from memory address 0x00000000.
• TBLOFF: Vector Table Base Offset
It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
Bit [29] determines whether the vector table is in the code or SRAM memory region:
0: Code.
1: SRAM.
It is sometimes called the TBLBASE bit.
Bit [29] determines whether the vector table is in the code or SRAM memory region:
0: Code.
1: SRAM.
It is sometimes called the TBLBASE bit.
Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the next
statement to give the information required for your implementation; the statement reminds the user of how to determine the
alignment requirement. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the
alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the alignment must be on a 64-word
boundary because the required table size is 37 words, and the next power of two is 64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
31
30
29
28
27
26
25
24
TBLOFF
23
22
21
20
19
18
17
16
TBLOFF
15
14
13
12
11
10
9
8
TBLOFF
7
6
5
4
3
2
1
0
TBLOFF
–