Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if 

WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by 

default and with a period set to a maximum.
When the WDRSTEN in the WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. 

The Reset State Manager manages the following priorities between the different reset sources, given in 

descending order:



General Reset



Backup Reset



Watchdog Reset



Software Reset



User Reset

Particular cases are listed below:



When in User Reset: 

̶

A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. 

̶

A software reset is impossible, since the processor reset is being activated. 



When in Software Reset: 

̶

A watchdog event has priority over the current state.

̶

The NRST has no effect. 



When in Watchdog Reset: 

̶

The processor reset is active and so a Software Reset cannot be programmed.

̶

A User Reset cannot be entered. 

Only if 

WDRPROC = 0

SLCK

periph_nreset

proc_nreset

wd_fault

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup 

= 2 cycles

Any

Freq.

RSTTYP

Any

XXX

0x2 = Watchdog Reset