Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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A Backup Reset occurs when the chip exits from Backup Mode. While exiting Backup Mode, the vddcore_nreset 

signal is asserted by the Supply Controller.
Field RSTTYP in the RSTC_SR is updated to report a Backup Reset.

The User Reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1. 

The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral 

Reset are asserted. 
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. 

The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, field RSTTYP in the RSTC_SR is loaded with the value 0x4, 

indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock 

cycles, as programmed in field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH 

because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. 

The Reset Controller offers several commands used to assert the different reset signals. These commands are 

performed by writing the Control Register (RSTC_CR) with the following bits at 1:



PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.



PERRST: Writing PERRST at 1 resets all the embedded peripherals  including the memory system, and, in 

particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.

Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and 

PROCRST set both at 1 simultaneously).

SLCK

periph_nreset

proc_nreset

NRST

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup 

= 2 cycles

Any

Freq.

Resynch.

2 cycles

RSTTYP

Any

XXX

Resynch.

2 cycles

0x4 = User Reset