Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

284

RSTC_SR

0x400E1404

Read-only

0: No high-to-low edge on NRST happened since the last read of RSTC_SR.
1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.

Registers the NRST Pin Level at Master Clock (MCK)

0: No software command is being performed by the reset controller. The reset controller is ready for a software command. 
1: A software reset command is being performed by the reset controller. The reset controller is busy.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

SRCMP

NRSTL

15

14

13

12

11

10

9

8

–

–

–

–

–

RSTTYP

7

6

5

4

3

2

1

0

–

–

–

–

–

–

–

URSTS

0

GENERAL_RST

First power-up Reset

1

BACKUP_RST

Return from Backup Mode

2

WDT_RST

Watchdog fault occurred

3

SOFT_RST

Processor reset required by the software

4

USER_RST

NRST pin detected low