Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

285

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

RSTC_MR

0x400E1408

Read/Write

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register 

(SYSC_WPMR).

0: The detection of a low level on the pin NRST does not generate a User Reset.
1: The detection of a low level on the pin NRST triggers a User Reset.

0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.

This field defines the external reset length. The external reset is asserted during a time of 2

(ERSTL+1)

 Slow Clock cycles. 

This allows assertion duration to be programmed between 60 µs and 2 seconds. Note that synchronization cycles must 

also be considered when calculating the actual reset length as previously described.

31

30

29

28

27

26

25

24

KEY

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

ERSTL

7

6

5

4

3

2

1

0

–

–

URSTIEN

–

–

–

URSTEN

0xA5

PASSWD

Writing any other value in this field aborts the write operation.
Always reads as 0.