Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The programmable 16-bit prescaler value can be configured in the field RTPRES of the Real-time Timer Mode 

Register (RTT_MR). 
Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a 

1 Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 2

32

 seconds, corresponding to 

more than 136 years, then roll over to 0. Bit RTTINC in the Real-time Timer Status Register (RTT_SR) is set each 

time there is a prescaler roll-over.
The real-time 32-bit counter can also be supplied by the RTC 1 Hz clock. This mode is interesting when the RTC 1 

Hz is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and 

RTT counters.
Setting bit RTC1HZ in the RTT_MR drives the 32-bit RTT counter from the RTC 1 Hz clock. In this mode, the 

RTPRES field has no effect on the 32-bit counter.
The prescaler roll-over generates an increment of the Real-time Timer counter if RTC1HZ = 0, else if RTC1HZ = 1, 

the Real-time Timer counter is incremented every second. Bit RTTINC is set independently from the 32-bit counter 

increment.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is 

achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status 

events because the Real-time Time Status Register (RTT_SR) is cleared two slow clock cycles after read. Thus if 

the RTT is configured to trigger an interrupt, the interrupt occurs two slow clock cycles after reading the RTT_SR. 

To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and 

re-enabled when the RTT_SR is cleared.
The current real-time value (CRTV) can be read at any time in the Real-time Timer Value Register (RTT_VR). As 

this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the 

same value to improve accuracy of the returned value.
The current value of the counter is compared with the value written in the Real-time Timer Alarm Register 

(RTT_AR). If the counter value matches the alarm, the bit ALMS in the RTT_SR is set. The RTT_AR is set to its 

maximum value (0xFFFF_FFFF) after a reset.
The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value in 

the RTT_AR.
The RTTINC bit can be used to start a periodic interrupt, the period being one second when the RTPRES field 

value = 0x8000 and the slow clock = 32.768 Hz.
The RTTINCIEN bit must be cleared prior to writing a new RTPRES value in the RTT_MR.
Reading the RTT_SR automatically clears the RTTINC and ALMS bits.
Writing the bit RTTRST in the RTT_MR immediately reloads and restarts the clock divider with the new 

programmed value. This also resets the 32-bit counter.
When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this 

module. This can be achieved by setting the RTTDIS bit in the RTT_MR.