Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

310

 RTC_SR

0x400E1478

 Read

-only 

0 (FREERUN): Time and calendar registers cannot be updated.
1 (UPDATE): Time and calendar registers can be updated.

0 (NO_ALARMEVENT): No alarm matching condition occurred.
1 (ALARMEVENT): An alarm matching condition has occurred.

0 (NO_SECEVENT): No second event has occurred since the last clear.
1 (SECEVENT): At least one second event has occurred since the last clear.

0 (NO_TIMEVENT): No time event has occurred since the last clear.
1 (TIMEVENT): At least one time event has occurred since the last clear.
The time event is selected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the following 

events: minute change, hour change, noon, midnight (day change).

0 (NO_CALEVENT): No calendar event has occurred since the last clear.
1 (CALEVENT): At least one calendar event has occurred since the last clear.
The calendar event is selected in the CALEVSEL field in the Control Register (RTC_CR) and can be any one of the follow-

ing events: week change, month change and year change.

0 (CORRECT): The internal free running counters are carrying valid values since the last read of the Status Register 

(RTC_SR).
1 (ERR_TIMEDATE): The internal free running counters have been corrupted (invalid date or time, non-BCD values) since 

the last read and/or they are still invalid.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

–

–

TDERR

CALEV

TIMEV

SEC

ALARM

ACKUPD