Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
329
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow
clock periods, depending on what the user selects. This can be configured by programming the SMSMPL field in
SUPC_SMMR.
Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by
Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by
factors of 2, 16 and 128, respectively, if the user does not need a continuous monitoring of the VDDIO power
supply.
A supply monitor detection either generates a reset of the core power supply or a wake-up of the core power
A supply monitor detection either generates a reset of the core power supply or a wake-up of the core power
supply. Generating a core reset when a supply monitor detection occurs is enabled by writing the SMRSTEN bit to
1 in SUPC_SMMR.
Waking up the core power supply when a supply monitor detection occurs can be enabled by writing the SMEN bit
Waking up the core power supply when a supply monitor detection occurs can be enabled by writing the SMEN bit
to 1 in the Supply Controller Wake-up Mode register (SUPC_WUMR).
The Supply Controller provides two status bits in the Supply Controller Status register for the supply monitor which
The Supply Controller provides two status bits in the Supply Controller Status register for the supply monitor which
determines whether the last wake-up was due to the supply monitor:
The SMOS bit provides real-time information, updated at each measurement cycle or updated at each Slow
Clock cycle, if the measurement is continuous.
The SMS bit provides saved information and shows a supply monitor detection has occurred since the last
read of SUPC_SR.
The SMS flag generates an interrupt if the SMIEN bit is set to 1 in SUPC_SMMR.
Figure 18-2.
Supply Monitor Status Bit and Associated Interrupt
18.3.5 Backup Power Supply Reset
18.3.5.1 Raising the Backup Power Supply
As soon as the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset
cell maintains its output low as long as VDDIO has not reached its target voltage. During this time, the Supply
Controller is entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is
released, a counter is started for five slow clock cycles, which is the time required for the 32 kHz RC oscillator to
stabilize.
After this time, the voltage regulator is enabled. The core power supply rises and the brownout detector provides
After this time, the voltage regulator is enabled. The core power supply rises and the brownout detector provides
the bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset
Supply Monitor ON
3.3 V
0 V
Threshold
SMS and SUPC interrupt
Read SUPC_SR
Periodic Sampling
Continuous Sampling (SMSMPL = 1)