Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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signal to the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow 

clock cycle.

The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described in 

. The vddcore_nreset signal is normally asserted before shutting down the core 

power supply and released as soon as the core power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:



a supply monitor detection



a brownout detection

The supply monitor is capable of generating a reset of the system. This is enabled by setting the SMRSTEN bit in 

SUPC_SMMR. 
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for 

a minimum of 1 slow clock cycle. 

Zero-Power Power-On

Reset Cell output

22 - 42 kHz RC

Oscillator output

Fast RC

Oscillator output

Backup Power Supply

vr_on

bodcore_in

vddcore_nreset

NRST

(no ext. drive assumed)

proc_nreset

Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 4 MHz.

periph_nreset

7 x Slow Clock Cycles

3 x Slow Clock

Cycles

2 x Slow Clock

Cycles

6.5 x Slow Clock

Cycles

T

ON

 Voltage

Regulator

Zero-Power POR

Core Power Supply

RSTC.ERSTL

(5 for startup slow RC + 2 for synchro.)

default = 2