Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
349
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
20.
Enhanced Embedded Flash Controller (EEFC)
20.1
Description
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal
bus.
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing,
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing,
locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the
embedded Flash descriptor definition that informs the system about the Flash organization, thus making the
software generic.
20.2
Embedded Characteristics
Interface of the Flash Block with the 32-bit Internal Bus
Increases Performance in Thumb-2 Mode with 128-bit or 64-bit-wide Memory Interface up to 120 MHz
Code Loop Optimization
256 Lock Bits, Each Protecting a Lock Region
GPNVMx General-purpose GPNVM Bits
One-by-one Lock Bit Programming
Commands Protected by a Keyword
Erase the Entire Flash
Erase by Plane
Erase by Sector
Erase by Pages
Possibility of Erasing before Programming
Locking and Unlocking Operations
Possibility to Read the Calibration Bits
20.3
Product Dependencies
20.3.1 Power Management
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller
has no effect on its behavior.
20.3.2 Interrupt Sources
The EEFC interrupt line is connected to the interrupt controller. Using the EEFC interrupt requires the interrupt
controller to be programmed first. The EEFC interrupt is generated only on FRDY bit rising.
Table 20-1.
Peripheral IDs
Instance
ID
EFC0
6
EFC1
7