Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

351

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

An optimized controller manages embedded Flash reads, thus increasing performance when the processor is 

running in Thumb-2 mode by means of the 128- or 64-bit-wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded 

Flash wraps around the address space and appears to be repeated within it.
The read operations can be performed with or without wait states. Wait states must be programmed in the field 

FWS (Flash Read Wait State) in the Flash Mode register (EEFC_FMR). Defining FWS as 0 enables the single-

cycle access of the embedded Flash. Refer to the Electrical Characteristics section for more details.

By default, the read accesses of the Flash are performed through a 128-bit wide memory interface. It improves 

system performance especially when 2 or 3 wait states are needed.
For systems requiring only 1 wait state, or to focus on current consumption rather than performance, the user can 

select a 64-bit wide memory access via the FAM bit in EEFC_FMR.
Refer to the Electrical Characteristics section for more details.

Code read optimization is enabled if the SCOD bit in EEFC_FMR is cleared.
A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential code fetch. 

Note:

Immediate consecutive code read accesses are not mandatory to benefit from this optimization.

The sequential code read optimization is enabled by default. If the SCOD bit in EEFC_FMR is set to 1, these 

buffers are disabled and the sequential code read is no longer optimized.
Another system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize loop code fetch. Refer to “Code 

Loop Optimization” on page 352 for more details. 

Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access.

Flash Access

Buffer 0 (128bits)

Master Clock

ARM Request

       (32-bit)

XXX

Data To ARM

Bytes 0-15

Bytes 16-31

Bytes 32-47

Bytes 0-15

Buffer 1 (128bits)

Bytes 32-47

Bytes 0-3

Bytes 4-7

Bytes 8-11

Bytes 12-15

Bytes 16-19

Bytes 20-23

Bytes 24-27

XXX

XXX

Bytes 16-31

@Byte 0

@Byte 4

@Byte 8

@Byte 12

@Byte 16

@Byte 20

@Byte 24

@Byte 28

@Byte 32

Bytes 28-31