Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to 

the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. 

Extra reads to EEFC_FRR return 0.

The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB 

bit command. The table below shows the bit implementation for each frequency:

The RC calibration for the 4 MHz is set to ‘1000000’.

When the security is enabled, access to the Flash, either through the JTAG/SWD interface or through the Fast 

Flash Programming interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
The security bit is GPNVM0.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is 

performed. When the security bit is deactivated, all accesses to the Flash are permitted.

Each part is programmed with a 128 bits unique identifier. It can be used to generate keys for example. To read 

the unique identifier, the sequence is:

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Send the Start read unique identifier command (STUI) by writing EEFC_FCR with the STUI command.

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When the unique identifier is ready to be read, the FRDY bit in EEFC_FSR falls.

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The unique identifier is located in the first 128 bits of the Flash memory mapping, thus, at the address 

0x00400000-0x004003FF.

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To stop the unique identifier mode, the user needs to send the Stop read unique identifier command (SPUI) 

by writing EEFC_FCR with the SPUI command.

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When the SPUI command has been performed, the FRDY bit in EEFC_FSR rises. If an interrupt was 

enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the interrupt controller is activated.

Note that during the sequence, the software cannot run out of Flash.

Each part contains a user signature of 512 bytes. It can be used for storage. Read, write and erase of this area is 

allowed.
To read the user signature, the sequence is as follows:

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Send the Start read user signature command (STUS) by writing EEFC_FCR with the STUS command.

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When the user signature is ready to be read, the FRDY bit in EEFC_FSR falls.

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The user signature is located in the first 512 bytes of the Flash memory mapping, thus, at the address 

0x00400000-0x004001FF.

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To stop the user signature mode, the user needs to send the Stop read user signature command (SPUS) by 

writing EEFC_FCR with the SPUS command.

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When the SPUI command has been performed, the FRDY bit in EEFC_FSR rises. If an interrupt was 

enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the interrupt controller is activated.

Note that during the sequence, the software cannot run out of Flash or the second plane in case of dual plane.

8 MHz output

[28 - 22]

12 MHz output

[38 - 32]