Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent 

to processor operations. The cache controller is activated with its configuration registers. The configuration 

interface is memory mapped in the private peripheral bus.
Use the following sequence to enable the cache controller.

1. Verify that the cache controller is disabled, reading the value of the CSTS (cache status) field of the CMCC_SR 

register.

2. Enable the cache controller, writing 1 to the CEN (cache enable) field of the CMCC_CTRL register.

If the contents seen by the cache has changed, the user needs to invalidate the cache entries. It can be done line 

by line or for all cache entries.

When an invalidate by line command is issued the cache controller resets the valid bit information of the decoded 

cache line. As the line is no longer valid the replacement counter points to that line.
Use the following sequence to invalidate one line of cache.

1. Disable the cache controller, writing 0 to the CEN field of the CMCC_CTRL register.

2. Check CSTS field of the CMCC_SR to verify that the cache is successfully disabled.

Cache
Controller

METADATA RAM

DATA RAM

TAG RAM

RAM
Interface

Cortex M Interface

Memory Interface

Registers
Interface

APB 
Interface

Cortex M Memory Interface Bus

System Memory Bus