Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
383
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
3. Perform an invalidate by line writing the bit set {index, way} in the CMCC_MAINT1 register.
4. Enable the cache controller, writing 1 to the CEN field of the CMCC_CTRL register.
4. Enable the cache controller, writing 1 to the CEN field of the CMCC_CTRL register.
22.4.2.2 Cache Invalidate All Operation
To invalidate all cache entries:
Write 1 to the INVALL field of the CMCC_MAINT0 register.
22.4.3 Cache Performance Monitoring
The Cortex-M cache controller includes a programmable 32-bit monitor counter. The monitor can be configured to
count the number of clock cycles, the number of data hits or the number of instruction hits.
Use the following sequence to activate the counter
Use the following sequence to activate the counter
1. Configure the monitor counter, writing the MODE field of the CMCC_CFG register.
2. Enable the counter, writing one to the MENABLE field of the CMCC_MEN register.
3. If required, reset the counter, writing one to the SWRST field of the CMCC_MCTRL register.
4. Check the value of the monitor counter, reading EVENT_CNT field of the CMCC_SR.
3. If required, reset the counter, writing one to the SWRST field of the CMCC_MCTRL register.
4. Check the value of the monitor counter, reading EVENT_CNT field of the CMCC_SR.