Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
385
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
22.5.1 Cache Controller Type Register
Name:
CMCC_TYPE
Address:
0x4007C000
Access:
Read
-only
• AP: Access Port Access Allowed
0: Access Port Access is disabled.
1: Access Port Access is enabled.
1: Access Port Access is enabled.
• GCLK: Dynamic Clock Gating Supported
0: Cache controller does not support clock gating.
1: Cache controller uses dynamic clock gating.
1: Cache controller uses dynamic clock gating.
• RANDP: Random Selection Policy Supported
0: Random victim selection is not supported.
1: Random victim selection is supported.
1: Random victim selection is supported.
• LRUP: Least Recently Used Policy Supported
0: Least Recently Used Policy is not supported.
1: Least Recently Used Policy is supported.
1: Least Recently Used Policy is supported.
• RRP: Random Selection Policy Supported
0: Random Selection Policy is not supported.
1: Random Selection Policy is supported.
1: Random Selection Policy is supported.
• WAYNUM: Number of Way
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
CLSIZE
CSIZE
7
6
5
4
3
2
1
0
LCKDOWN
WAYNUM
RRP
LRUP
RANDP
GCLK
AP
Value
Name
Description
0
DMAPPED
Direct Mapped Cache
1
ARCH2WAY
2-WAY set associative
2
ARCH4WAY
4-WAY set associative
3
ARCH8WAY
8-WAY set associative