Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

433

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

Name:

MATRIX_SCFG0..MATRIX_SCFG4

0x400E0240

Read/Write 

When the SLOT_CYCLE limit is reach for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small. An unreasonably small value will break every burst and the Bus Matrix will spend its 

time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.

This is the number of the default master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a mas-

ter which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

ARBT

23

22

21

20

19

18

17

16

–

–

–

FIXED_DEFMSTR

DEFMSTR_TYPE

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

SLOT_CYCLE

0

NO_DEFAULT

At the end of current slave access, if no other master request is pending, the slave is 

disconnected from all masters.
This results in having a one cycle latency for the first access of a burst transfer or for a 

single access.

1

LAST

At the end of current slave access, if no other master request is pending, the slave 

stays connected to the last master having accessed it.
This results in not having the one cycle latency when the last master tries to access the 

slave again.

2

FIXED

At the end of the current slave access, if no other master request is pending, the slave 

connects to the fixed master the number that has been written in the 

FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master tries to access 

the slave again.

0

ROUND_ROBIN

Round-robin arbitration

1

FIXED_PRIORITY

Fixed priority arbitration