Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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The NRD signal is characterized by a setup timing, a pulse width and a hold timing.

1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge;

2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge;
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.

Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:

1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 

2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.

The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on 

the address bus to the point where address may change. The total read cycle time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD 
= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. 

To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold 

timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE 
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE

A[23:0]

NCS

NRD_SETUP

NRD_PULSE

NRD_HOLD

MCK

NRD

D[7:0]

NCS_RD_SETUP

NCS_RD_PULSE

NCS_RD_HOLD

NRD_CYCLE