Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal 

after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 454. 
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable 

behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For 

external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and 

NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the 

address bus.

The external data bus D[7:0] can be scrambled in order to prevent intellectual property data located in off-chip 

memories from being easily recovered by analyzing data at the package pin level of either microcontroller or 

memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2. These key 

registers are only accessible in write mode.
The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip 

memory. Any data scrambled with a given key cannot be recovered if the key is lost.
The scrambling/unscrambling function can be enabled or disabled by programming the SMC_OCMS register.
When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the 

OCMS field in the SMC_OCMS registers.

Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention 

or operation conflict.

The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that 

there is no bus contention between the de-activation of one device and the activation of the next one. 
During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1.

 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.