Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

452

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All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according 

to their type. 
The SMC_SETUP register groups the definition of all setup parameters:

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 NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP

The SMC_PULSE register groups the definition of all pulse parameters:

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 NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE

The SMC_CYCLE register groups the definition of all cycle parameters:

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 NRD_CYCLE, NWE_CYCLE

 shows how the timing parameters are coded and their permitted range. 

 gives the default value of timing parameters at reset.

The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE 

parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC. 
For read operations: 
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface 

because of the propagation delay of theses signals through external logic and pads. If positive setup and hold 

values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews 

between address, NCS and NRD signals.

setup [5:0]

6

128 x setup[5] + setup[4:0]

0 ≤ ≤ 31

0 ≤ ≤ 128+31

pulse [6:0]

7 

256 x pulse[6] + pulse[5:0]

0 ≤ ≤ 63

0 ≤ ≤ 256+63

cycle [8:0]

9

256 x cycle[8:7] + cycle[6:0]

0 ≤ ≤ 127

0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127

SMC_SETUP

0x01010101

All setup timings are set to 1

SMC_PULSE

0x01010101

All pulse timings are set to 1

SMC_CYCLE

0x00030003

The read and write operation last 3 Master Clock 

cycles and provide one hold cycle

WRITE_MODE

1

Write is controlled with NWE

READ_MODE

1

Read is controlled with NRD