Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

Product codes
ATSAM4S-WPIR-RD
Page of 1231
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
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Figure 26-16. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle
26.10.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface. 
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state 
before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load 
the new set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before 
and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip 
Select Wait State is applied.
On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload 
Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
26.10.3.1User Procedure
To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the 
user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in 
the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on 
the mode parameters. 
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if 
accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while 
fetching the code from a memory connected on this CS, may lead to unpredictable behavior. The instructions used 
to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory 
connected to another CS.
A[25:2]
write cycle
(WRITE_MODE = 1)
Early Read
wait state
MCK
NRD
internal write controlling signal
external write controlling signal
(NWE)
D[7:0]
read cycle
no hold
read setup = 1
(READ_MODE = 0 or READ_MODE = 1)