Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
458
Figure 26-17. TDF Period in NRD Controlled Read Access (TDF = 2)
Figure 26-18. TDF Period in NCS Controlled Read Operation (TDF = 3)
26.11.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip
Select 0. Chip Select 0 has been programmed with:
NCS
NRD controlled read operation
tpacc
MCK
NRD
D[7:0]
TDF = 2 clock cycles
A[23:0]
NCS
TDF = 3 clock cycles
tpacc
MCK
D[7:0]
NCS controlled read operation
A[23:0]
NRD