Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
506
processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the
PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC Master Clock
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC Master Clock
Register (PMC_MCKR).
It is forbidden to change the 4/8/12 MHz fast RC oscillator, or the main selection in CKGR_MOR register while the
It is forbidden to change the 4/8/12 MHz fast RC oscillator, or the main selection in CKGR_MOR register while the
master clock source is the PLL and the PLL reference clock is the fast RC oscillator.
The user must:
The user must:
Switch on the main RC oscillator by writing 1 in CSS field of PMC_MCKR.
Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR.
Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
Wait for LOCK flag in PMC_SR.
Switch back to PLL by writing the appropriate value to CSS field of PMC_MCKR.