Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
508
29.3
Block Diagram
Figure 29-1.
General Clock Block Diagram
29.4
Master Clock Controller
The Master Clock Controller provides selection and division of the master clock (MCK). MCK is the clock provided
to all the peripherals. The master clock is selected from one of the clocks provided by the Clock Generator.
Selecting the slow clock provides a slow clock signal to the whole device. Selecting the main clock saves power
Selecting the slow clock provides a slow clock signal to the whole device. Selecting the main clock saves power
consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler.
The master clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master
The master clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master
Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and
the division by 3. The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in PMC_SR. It reads 0
Each time PMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in PMC_SR. It reads 0
until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor.
This feature is useful when switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
USB Clock
UDPCK
Management
Controller
Main Clock
MAINCK
MAINCK
PLLA Clock
PLLACK
PLLACK
Control
Status
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
MOSCSEL
PLLA and
Divider /2
Divider /2
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
Embedded
32 kHz RC
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
PLLB Clock
PLLBCK
PLLBCK
0
1
0
1
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1, /2, /3, /4, /8,
/16, /32, /64
HCLK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
(PMC_MCKR)
ON/OFF
Prescaler
/1, /2, /4, /8,
/16, /32, /64
/16, /32, /64
pck[..]
PLLBCK
ON/OFF
FCLK
SysTick
Divider
/8
SLCK
MAINCK
PLLACK
PLLBCK
Processor clock
Free Running Clock
Master Clock
PLLB and
Divider /2
Divider
/1, /2, /3,... /16
USB Clock Controller (PMC_USB)
PLLBCK
Embedded
4/8/12 MHz
Fast
RC Oscillator
Programmable Clock Controller
(PMC_PCKx)
(PMC_PCKx)
PRES
USBDIV
PLLADIV2
PLLBDIV2
PRES
USBS
PLLACK
CSS
ON/OFF
CSS
MCK
Clock Generator
XTALSEL
Power
Slow Clock
Peripherals
Clock Controller
(PMC_PCERx)
Clock Controller
(PMC_PCERx)
PMC_MCKR
PMC_MCKR
CKGR_MOR