Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
531
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
29.17.9 PMC Clock Generator PLLA Register
Name:
CKGR_PLLAR
Address:
0x400E0428
Access:
Read/Write
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning:
Warning:
Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
This register can only be written if the WPEN bit is cleared in
• DIVA: PLLA Front_End Divider
0: Divider output is stuck at 0 and PLLA is disabled.
1: Divider is bypassed (divide by 1) PLLA is enabled
2 up to 255 = clock is divided by DIVA
1: Divider is bypassed (divide by 1) PLLA is enabled
2 up to 255 = clock is divided by DIVA
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0: The PLLA is deactivated (PLLA also disabled if DIVA = 0).
4 up to 62 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
4 up to 62 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
31
30
29
28
27
26
25
24
–
–
ONE
–
–
MULA
23
22
21
20
19
18
17
16
MULA
15
14
13
12
11
10
9
8
–
–
PLLACOUNT
7
6
5
4
3
2
1
0
DIVA