Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
532
29.17.10PMC Clock Generator PLLB Register
Name:
CKGR_PLLBR
Address:
0x400E042C
Access:
Read/Write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in
This register can only be written if the WPEN bit is cleared in
• DIVB: PLLB Front-End Divider
0: Divider output is stuck at 0 and PLLB is disabled.
1= Divider is bypassed (divide by 1)
2 up to 255 = clock is divided by DIVB
1= Divider is bypassed (divide by 1)
2 up to 255 = clock is divided by DIVB
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0: The PLLB is deactivated (PLLB also disabled if DIVB = 0).
4 up to 62 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
4 up to 62 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
31
30
29
28
27
26
25
24
–
–
–
–
–
MULB
23
22
21
20
19
18
17
16
MULB
15
14
13
12
11
10
9
8
–
–
PLLBCOUNT
7
6
5
4
3
2
1
0
DIVB