Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the 

pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 

in addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on 

peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.

When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of 

the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 

and PIO_ABCDSR2 determines whether the pin is driven or not. 
When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing 

the Output Enable register (PIO_OER) and Output Disable register (PIO_ODR). The results of these write 

operations are detected in the Output Status register (PIO_OSR). When a bit in this register is at zero, the 

corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the 

PIO Controller.
The level driven on an I/O line can be determined by writing in the Set Output Data register (PIO_SODR) and the 

Clear Output Data register (PIO_CODR). These write operations, respectively, set and clear the Output Data 

Status register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and 

PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to 

a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO 

Controller. 
Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level 

driven on the I/O line.

Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by 

using PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different 

registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to 

PIO_ODSR. Only bits unmasked by the Output Write Status register (PIO_OWSR) are written. The mask bits in 

PIO_OWSR are set by writing to the Output Write Enable register (PIO_OWER) and cleared by writing to the 

Output Write Disable register (PIO_OWDR).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.

Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits 

several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor 

(or enabling of the internal one) is generally required to guarantee a high level on the line.
The multi-drive feature is controlled by the Multi-driver Enable register (PIO_MDER) and the Multi-driver Disable 

register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or 

assigned to a peripheral function. The Multi-driver Status register (PIO_MDSR) indicates the pins that are 

configured to support external drivers.
After reset, the multi-drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.

 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing 

PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. 

 also shows when 

the feedback in the Pin Data Status register (PIO_PDSR) is available.