Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines 

regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a 

peripheral. 
Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the 

levels present on the I/O line at the time the clock was disabled.

Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 master clock (MCK) and the debouncing filter can 

filter a pulse of less than 1/2 period of a programmable divided slow clock.
The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock 

Disable register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable register (PIO_IFSCER). Writing 

PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status register 

(PIO_IFSCSR).
The current selection status can be checked by reading the register PIO_IFSCSR.



If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.



If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable 

divided slow clock period.

For the debouncing filter, the period of the divided slow clock is performed by writing in the DIV field of the Slow 

Clock Divider register (PIO_SCDR. 
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock 

cycle (selected clock represents MCK or divided slow clock depending on PIO_IFSCDR and PIO_IFSCER 

programming) is automatically rejected, while a pulse with a duration of one selected clock (MCK or divided slow 

clock) cycle or more is accepted. For pulse durations between 1/2 selected clock cycle and one selected clock 

cycle, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for 

a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch to be reliably filtered out, its 

duration must not exceed 1/2 selected clock cycle.
The filters also introduce some latencies, illustrated in 

 and 

2 cycles

APB Access

2 cycles

APB Access

MCK

Write PIO_SODR

Write PIO_ODSR at 1

PIO_ODSR

PIO_PDSR

Write PIO_CODR

Write PIO_ODSR at 0