Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

622



an external clock received on the RK I/O pad



the transmitter clock



the internal clock divider

Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can 

generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers. 

The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 

4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is 

provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used 

and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided 

by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures 

a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.

MCK

Divided Clock

Clock Divider

/ 2

12-bit Counter

SSC_CMR

Master Clock

Divided Clock

DIV = 1

Master Clock

Divided Clock

DIV = 3

Divided Clock Frequency = MCK/2

Divided Clock Frequency = MCK/6