Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

625

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

A received frame is triggered by a start event and can be followed by synchronization data before data 

transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 626.
The frame synchronization is configured setting the Receive Frame Mode Register (

SSC_RFMR

Sync” on page 628.
The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the 

SSC_RCMR. The data is transferred from the shift register depending on the data format selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is 

set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of 

the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the 

RHR register.

Transmit Shift Register

TD

SSC_TFMR.FSLEN

SSC_TFMR.DATLEN

SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.DATDEF
SSC_TFMR.MSBF

SSC_TCMR.STTDLY != 0

SSC_TFMR.FSDEN

1

0

TX Controller

SSC_TCMR.START

RF

Start

Selector

TXEN

RX Start

TXEN

RF

Start

Selector

RXEN

RC0R

TX Start

TX Start

Transmitter Clock

TX Controller counter reached STTDLY

SSC_RCMR.START

SSC_THR

SSC_TSHR

SSC_CRTXEN

SSC_SRTXEN

SSC_CRTXDIS