Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
666
33.6.2 Power Management
The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SPI clock.
33.6.3 Interrupt
The SPI interface has an interrupt line connected to the interrupt controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
33.6.4 Peripheral DMA Controller (PDC)
The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full
description of the PDC, refer to the corresponding section in the full datasheet.
33.7
Functional Description
33.7.1 Modes of Operation
The SPI operates in Master mode or in Slave mode.
The SPI operates in Master mode by writing to 1 the MSTR bit in the SPI Mode register (SPI_MR):
̶
The pins NPCS0 to NPCS3 are all configured as outputs
̶
The SPCK pin is driven
̶
The MISO line is wired on the receiver input
̶
The MOSI line is driven as an output by the transmitter.
The SPI operates in Slave mode if the MSTR bit in SPI_MR is written to 0:
̶
The MISO line is driven by the transmitter output
̶
The MOSI line is wired on the receiver input
̶
The SPCK pin is driven by the transmitter to synchronize the receiver.
SPI
NPCS0
PA11
A
SPI
NPCS1
PA9
B
SPI
NPCS1
PA31
A
SPI
NPCS1
PB14
A
SPI
NPCS1
PC4
B
SPI
NPCS2
PA10
B
SPI
NPCS2
PA30
B
SPI
NPCS2
PB2
B
SPI
NPCS3
PA3
B
SPI
NPCS3
PA5
B
SPI
NPCS3
PA22
B
SPI
SPCK
PA14
A
Table 33-2.
I/O Lines
Table 33-3.
Peripheral IDs
Instance
ID
SPI
21