Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
667
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
̶
The NPCS0 pin becomes an input, and is used as a slave select signal (NSS)
̶
The pins NPCS0 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is
activated only in Master mode.
33.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These
two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two
parameters has two possible states, resulting in four possible combinations that are incompatible with one another.
Consequently, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves
are connected and require different configurations, the master must reconfigure itself each time it needs to
communicate with a different slave.
shows the four modes and corresponding parameter settings.
and
show examples of data transfers.
Figure 33-3.
SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Table 33-4.
SPI Bus Protocol Mode
SPI Mode
CPOL
NCPHA
Shift SPCK Edge
Capture SPCK Edge
SPCK Inactive Level
0
0
1
Falling
Rising
Low
1
0
0
Rising
Falling
Low
2
1
1
Rising
Falling
High
3
1
0
Falling
Rising
High
6
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined.
1
2
3
4
5
7
8
6