Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

682

 SPI_MR

0x40008004

Read-write 

This register can only be written if the WPEN bit is cleared in 



0: SPI is in Slave mode. 
1: SPI is in Master mode.



0: Fixed Peripheral Select.
1: Variable Peripheral Select.



0: The chip selects are directly connected to a peripheral device.
1: The four NPCS chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15Chip Select signals can be generated with the four NPCS lines using an external 4- to 

16-bit decoder. The Chip Select registers define the characteristics of the 15 chip selects, with the following rules:

SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.



0: Mode fault detection is enabled. 
1: Mode fault detection is disabled.



0: No Effect. In Master mode, a transfer can be initiated regardless of the SPI_RDR state.
1: In Master mode, a transfer can start only if the SPI_RDR is empty, i.e. does not contain any unread data. This mode pre-

vents overrun error in reception.



0: Local loopback path disabled. 

31

30

29

28

27

26

25

24

DLYBCS

23

22

21

20

19

18

17

16

–

–

–

–

PCS

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

LLB

–

WDRBT

MODFDIS

–

PCSDEC

PS

MSTR