Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
720
Figure 34-29. Clock Synchronization in Write Mode
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the
mechanism is finished.
34.10.5.5Reversal after a Repeated Start
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
describes the repeated start + reversal from Read to Write mode.
Figure 34-30. Repeated Start + Reversal from Read to Write Mode
Note:
1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
Rd DATA0
Rd DATA1
Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA1
DATA2
SCL is stretched on the last bit of DATA1
As soon as a START is detected
TWCK
TWD
TWI_RHR
CLOCK is tied low by the TWI as long as RHR is full
DATA0 is not read in the RHR
ADR
S
SADR
W
A
DATA0
A
A
DATA2
DATA1
S
NA
S
SADR
R
A
DATA0
A
DATA1
SADR
Sr
NA
W
A
DATA2
A
DATA3
A
P
Cleared after read
DATA0
DATA1
DATA2
DATA3
SVACC
SVREAD
TWD
TWI_THR
TWI_RHR
EOSACC
TXRDY
RXRDY
TXCOMP
As soon as a START is detected