Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The master initiates the communication by a write command and finishes it by a read command. 

describes the repeated start + reversal from Write to Read mode.

Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before 

the ACK.

2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.

The use of the PDC significantly reduces the CPU load.

The following procedure shows an example to transmit data with PDC.

1. Initialize the transmit PDC (memory pointers, transfer size).

2. Start the transfer by setting the PDC TXTEN bit.
3. Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt.
4. Disable the PDC by setting the PDC TXTDIS bit.
5. (Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.

The following procedure shows an example to transmit data with PDC where the number of characters to receive 

is known.

1. Initialize the receive PDC (memory pointers, transfer size).

2. Set the PDC RXTEN bit.
3. Wait for the PDC ENDRX flag either by using polling method or ENDRX interrupt.
4. Disable the PDC by setting the PDC RXTDIS bit.
5. (Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.

S

SADR

W

A

DATA0

A

DATA1

SADR

Sr

A

R

A

DATA2

A

DATA3

NA

P

Cleared after read

DATA0

DATA2

DATA3

DATA1

TXCOMP

TXRDY

RXRDY

As soon as a START is detected

Read TWI_RHR

SVACC

SVREAD

TWD

TWI_RHR

TWI_THR

EOSACC