Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

Product codes

ATSAM4S-WPIR-RD

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

766

Figure 36-7.

Transmitter Status

36.7.3.2 Manchester Encoder

When the Manchester encoder is in use, characters transmitted through the USART are encoded based on

biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on

polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus,

a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ

signal (2x) but the receiver has more error control since the expected input must show a change at the center of a

bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01

01 01 10, assuming the default polarity of the encoder.

Figure 36-8

illustrates this coding scheme.

Figure 36-8.

NRZ to Manchester Encoding

The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start

frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a

predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the

preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following

sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register,

the field TX_PL is used to configure the preamble length.

Figure 36-9

illustrates and defines the valid patterns. To

improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If

the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is

encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero

transition and a logic zero is encoded with a zero-to-one transition.

TXD

Start

Bit

Parity

Bit

Stop

Bit

Baud Rate

Clock

Start

Bit

Write

US_THR

Parity

Bit

Stop

Bit

TXRDY

TXEMPTY

NRZ

encoded

data

Manchester

encoded

data

Txd