Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger 

clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is 

one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. 

If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened 

by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current 

period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are 

automatically taken.

If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD 

input line. The oversampling is either 16 or 8 times the baud rate clock, depending on the OVER bit in the US_MR.
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected 

and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER to 0), a start is detected at the eighth sample to 0. Then, data bits, parity bit and 

stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER to 1), a start bit is detected 

at the fourth sample to 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.

Manchester

encoded

data

Txd

SFD

DATA

One bit start frame delimiter

Preamble Length 

is set to 0

Manchester

encoded

data

Txd

SFD

DATA

Command Sync

start frame delimiter

Manchester

encoded

data

Txd

SFD

DATA

Data Sync

start frame delimiter

RXD

Oversampling

 16x Clock

Sampling 

point

Expected edge

Tolerance

Synchro.

Jump

Sync

Jump

Synchro.

Error

Synchro.

Error