Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with 

external devices in master or slave mode. It also enables communication between processors if an external 

processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a 

data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as 

“slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one 

master may simultaneously shift data into multiple slaves. (Multiple master protocol is the opposite of single 

master protocol, where one CPU is always the master while all of the others are always slaves.) However, only 

one slave may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI master mode can 

address only one SPI slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:



master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of 

the slave.



master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.



Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The 

master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is 

transmitted.



Slave Select (NSS): This control line allows the master to select or deselect the slave.

The USART can operate in SPI master mode or in SPI slave mode.
Operation in SPI master mode is programmed by writing 0xE to the USART_MODE field in US_MR. In this case 

the SPI lines must be connected as described below:



The MOSI line is driven by the output pin TXD



The MISO line drives the input pin RXD



The SCK line is driven by the output pin SCK



The NSS line is driven by the output pin RTS

Operation in SPI slave mode is programmed by writing to 0xF the USART_MODE field in US_MR. In this case the 

SPI lines must be connected as described below:



The MOSI line drives the input pin RXD



The MISO line is driven by the output pin TXD



The SCK line drives the input pin SCK



The NSS line drives the input pin CTS

In order to avoid unpredicted behavior, any change of the SPI mode must be followed by a software reset of the 

transmitter and of the receiver (except the initial configuration after a hardware reset). (See 

In SPI mode, the baud rate generator operates in the same way as in USART synchronous mode: See “Baud Rate 

in Synchronous Mode or SPI Mode” on page 763. However, there are some restrictions:
In SPI master mode:



The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to ‘1’ in the 

US_MR, in order to generate correctly the serial clock on the SCK pin.



To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior 

or equal to 6.