Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

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If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a 

50:50 mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).

In SPI slave mode:

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The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR. 

Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal 

on the USART SCK pin.

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To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at 

least 6 times lower than the system clock.

Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL 

and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the US_MR. The nine bits are 

selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI mode 

(master or slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the 

CPOL bit in the US_MR. The clock phase is programmed with the CPHA bit. These two parameters determine the 

edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible 

states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair 

must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different 

configurations, the master must reconfigure itself each time it needs to communicate with a different slave.

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