Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

the receiver side is not ready (character not read). When WRDBT equals 0, the character is transmitted whatever 

the receiver status. If WRDBT is set to 1, the transmitter waits for the Receive Holding register (US_RHR) to be 

read before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character loss) on the 

receiver side.
The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is 

empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the 

current character processing is completed, the last character written in US_THR is transferred into the Shift 

register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while 

TXRDY is low has no effect and the written character is lost.
If the USART is in SPI slave mode and if a character must be sent while the US_THR is empty, the UNRE 

(Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is 

cleared by writing a one to the RSTSTA (Reset Status) bit in US_CR.
In SPI master mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before the transmission of 

the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) 

is always released between each character transmission and a minimum delay of 3 Tbits always inserted. 

However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the 

slave select line (NSS) can be forced at low level by writing a one to the RTSEN bit in the US_CR. The slave select 

line (NSS) can be released at high level only by writing a one to the RTSDIS bit in the US_CR (for example, when 

all data have been transferred to the slave device).
In SPI slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a 

character transmission but only a low level. However, this low level must be present on the slave select line (NSS) 

at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.

When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the 

RXRDY bit in the Status register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE 

(Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The 

OVRE bit is cleared by writing a one to the RSTSTA (Reset Status) bit the US_CR. 
To ensure correct behavior of the receiver in SPI slave mode, the master device sending the frame must ensure a 

minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the 

slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be 

present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB 

bit.

Because the receiver baud rate clock is active only during data transfers in SPI mode, a receiver timeout is 

impossible in this mode, whatever the time-out value is (field TO) in the US_RTOR.

The USART can be programmed to operate in three different test modes. The internal loopback capability allows 

on-board diagnostics. In loopback mode, the USART interface pins are disconnected or not and reconfigured for 

loopback internally or externally. 

Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.