Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

949

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

Before enabling the channels, they must have been configured by the software application:



Unlock User Interface by writing the WPCMD field in the PWM_WPCR.



Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required).



Selection of the clock for each channel (CPRE field in PWM_CMRx)



Configuration of the waveform alignment for each channel (CALG field in PWM_CMRx)



Selection of the counter event selection (if CALG = 1) for each channel (CES field in PWM_CMRx)



Configuration of the output waveform polarity for each channel (CPOL bit in PWM_CMRx)



Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx 

register is possible while the channel is disabled. After validation of the channel, the user must use 

PWM_CPRDUPDx register to update PWM_CPRDx as explained below.



Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register). Writing in 

PWM_CDTYx register is possible while the channel is disabled. After validation of the channel, the user 

must use PWM_CDTYUPDx register to update PWM_CDTYx as explained below.



Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if enabled (DTE bit 

in the PWM_CMRx). Writing in the PWM_DTx register is possible while the channel is disabled. After 

validation of the channel, the user must use PWM_DTUPDx register to update PWM_DTx



Selection of the synchronous channels (SYNCx in the PWM_SCM register)



Selection of the moment when the WRDY flag and the corresponding PDC transfer request are set (PTRM 

and PTRCS in the PWM_SCM register)



Configuration of the update mode (UPDM in PWM_SCM register)



Configuration of the update period (UPR in PWM_SCUP register) if needed



Configuration of the comparisons (PWM_CMPVx and PWM_CMPMx)



Configuration of the event lines (PWM_ELMRx)



Configuration of the fault inputs polarity (FPOL in PWM_FMR)



Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and PWM_FPE1)



Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1, and writing WRDYE, ENDTXE, 

TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2)



Enable of the PWM channels (writing CHIDx in the PWM_ENA register)

The large number of source clocks can make selection difficult. The relationship between the value in the 

 (PWM_CPRDx) and the 

the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle 

quantum cannot be lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM 

accuracy. 
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value from between 1 up to 

14 in PWM_CDTYx. The resulting duty-cycle quantum cannot be lower than 1/15 of the PWM period.

It is possible to modulate the output waveform duty-cycle, period and dead-times. 
To prevent unexpected output waveform, the user must use the 

 (PWM_CPRDUPDx) and the 

 (PWM_DTUPDx) to change waveform parameters while the channel is still enabled.