Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
951
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
(PWM_SCUPUPD) to change the update period of synchronous
channels while they are still enabled. This register holds the new value until the end of the update period of
synchronous channels (when UPRCNT is equal to UPR in PWM_SCUP) and the end of the current PWM period,
then updates the value for the next period.
Note:
If the update register PWM_SCUPUPD is written several times between two updates, only the last written value is
taken into account.
Note:
Changing the update period does make sense only if there is one or more synchronous channels and if the update
method 1 or 2 is selected (UPDM = 1 or 2 in
Figure 39-18. Synchronized Update of Update Period Value of Synchronous Channels
39.6.5.5 Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled
).
To prevent unexpected comparison match, the user must use the
(PWM_CMPVUPDx) and the
(PWM_CMPMUPDx) to change
respectively the comparison values and the comparison configurations while the channel 0 is still enabled. These
registers hold the new values until the end of the comparison update period (when CUPRCNT is equal to CUPR in
(PWM_CMPMx) and the end of the current PWM period, then update the
values for the next period.
CAUTION:
CAUTION:
The write of the register PWM_CMPVUPDx must be followed by a write of the register
PWM_CMPMUPDx.
Note:
If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times between two updates,
only the last written value are taken into account.
End of PWM period and
end of Update Period
of Synchronous Channels
end of Update Period
of Synchronous Channels
PWM_SCUPUPD Value
User's Writing
PWM_SCUP