Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
130
32072H–AVR32–10/2012
AT32UC3A3
12. Flash Controller (FLASHC)
Rev: 2.2.1.3
12.1
Features
•
Controls flash block with dual read ports allowing staggered reads.
•
Supports 0 and 1 wait state bus access.
•
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
•
32-bit HSB interface for reads from flash array and writes to page buffer.
•
32-bit PB interface for issuing commands to and configuration of the controller.
•
16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16)
pages.
•
Regions can be individually protected or unprotected.
•
Additional protection of the Boot Loader pages.
•
Supports reads and writes of general-purpose NVM bits.
•
Supports reads and writes of additional NVM pages.
•
Supports device protection through a security bit.
•
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
•
Interface to Power Manager for power-down of flash-blocks in sleep mode.
•
12.2
Overview
The flash controller (None) interfaces a flash block with the 32-bit internal HSB bus. Perfor-
mance for uncached systems with high clock-frequency and one wait state is increased by
placing words with sequential addresses in alternating flash subblocks. Having one read inter-
face per subblock allows them to be read in parallel. While data from one flash subblock is being
output on the bus, the sequential address is being read from the other flash subblock and will be
ready in the next clock cycle.
mance for uncached systems with high clock-frequency and one wait state is increased by
placing words with sequential addresses in alternating flash subblocks. Having one read inter-
face per subblock allows them to be read in parallel. While data from one flash subblock is being
output on the bus, the sequential address is being read from the other flash subblock and will be
ready in the next clock cycle.
The controller also manages the programming, erasing, locking and unlocking sequences with
dedicated commands.
dedicated commands.
12.3
Product dependencies
12.3.1
Power Manager
The FLASHC has two bus clocks connected: One High speed bus clock (CLK_FLASHC_HSB)
and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are generated by the Power
m a n a g e r . B o t h c l o c k s a r e t u r n e d o n b y d e f a u l t , b u t t h e u s e r h a s t o e n s u r e t h a t
CLK_FLASHC_HSB is not turned off before reading the flash or writing the pagebuffer and that
CLK_FLASHC_PB is not turned of before accessing the FLASHC configuration and control
registers.
and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are generated by the Power
m a n a g e r . B o t h c l o c k s a r e t u r n e d o n b y d e f a u l t , b u t t h e u s e r h a s t o e n s u r e t h a t
CLK_FLASHC_HSB is not turned off before reading the flash or writing the pagebuffer and that
CLK_FLASHC_PB is not turned of before accessing the FLASHC configuration and control
registers.
12.3.2
Interrupt Controller
The FLASHC interrupt lines are connected to internal sources of the interrupt controller. Using
FLASHC interrutps requires the interrupt controller to be programmed first.
FLASHC interrutps requires the interrupt controller to be programmed first.