Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
131
32072H–AVR32–10/2012
AT32UC3A3
12.4
Functional description
12.4.1
Bus interfaces
The None has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash
array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands
and control to and reading status from the controller.
array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands
and control to and reading status from the controller.
12.4.2
Memory organization
To maximize performance for high clock-frequency systems, None interfaces to a flash block
with two read ports. The flash block has several parameters, given by the design of the flash
block. Refer to the “Memories” chapter for the device-specific values of the parameters.
with two read ports. The flash block has several parameters, given by the design of the flash
block. Refer to the “Memories” chapter for the device-specific values of the parameters.
• p pages (FLASH_P)
• w words in each page and in the page buffer (FLASH_W)
• pw words in total (FLASH_PW)
• f general-purpose fuse bits (FLASH_F)
• 1 security fuse bit
• 1 User Page
12.4.3
User page
The User page is an additional page, outside the regular flash array, that can be used to store
various data, like calibration data and serial numbers. This page is not erased by regular chip
erase. The User page can only be written and erased by proprietary commands. Read accesses
to the User page is performed just as any other read access to the flash. The address map of the
User page is given in
various data, like calibration data and serial numbers. This page is not erased by regular chip
erase. The User page can only be written and erased by proprietary commands. Read accesses
to the User page is performed just as any other read access to the flash. The address map of the
User page is given in
12.4.4
Read operations
The None provides two different read modes:
• 0 wait state (0ws) for clock frequencies < (access time of the flash plus the bus delay)
• 1 wait state (1ws) for clock frequencies < (access time of the flash plus the bus delay)/2
Higher clock frequencies that would require more wait states are not supported by the flash
controller.
controller.
The programmer can select the wait states required by writing to the FWS field in the Flash Con-
trol Register (FCR). It is the responsibility of the programmer to select a number of wait states
compatible with the clock frequency and timing characteristics of the flash block.
trol Register (FCR). It is the responsibility of the programmer to select a number of wait states
compatible with the clock frequency and timing characteristics of the flash block.
In 0ws mode, only one of the two flash read ports is accessed. The other flash read port is idle.
In 1ws mode, both flash read ports are active. One read port reading the addressed word, and
the other reading the next sequential word.
In 1ws mode, both flash read ports are active. One read port reading the addressed word, and
the other reading the next sequential word.
If the clock frequency allows, the user should use 0ws mode, because this gives the lowest
power consumption for low-frequency systems as only one flash read port is read. Using 1ws
mode has a power/performance ratio approaching 0ws mode as the clock frequency
approaches twice the max frequency of 0ws mode. Using two flash read ports use twice the
power, but also give twice the performance.
power consumption for low-frequency systems as only one flash read port is read. Using 1ws
mode has a power/performance ratio approaching 0ws mode as the clock frequency
approaches twice the max frequency of 0ws mode. Using two flash read ports use twice the
power, but also give twice the performance.