Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

When switching from slow clock mode to the normal mode, the current slow clock mode transfer
is completed at high clock rate, with the set of slow clock mode parameters. See 

. The external device may not be fast enough to support such timings.

 illustrates the recommended procedure to properly switch from one

mode to the other.

Figure 15-31. Clock Rate Transition Occurs while the SMC is Performing a Write Operation 

CLK_SMC

A[AD_MSB:2]

NBS0, NBS1, 

A0, A1

NCS

NWE

Slow Clock Mode

Internal signal from PM

This write cycle finishes with the slow clock mode set

of parameters after the clock rate transition

NWECYCLE = 3

SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE

1

1

1

1

1

1

2

3

2

NWECYCLE = 7

NORMAL MODE WRITE

Slow clock mode transition is detected:

Reload Configuration Wait State